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Preliminary
XRT59L91
Single-Chip E1 Line Interface Unit
October 1999-1
FEATURES
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Complete E1 (CEPT) line interface unit (Transmitter and Receiver) Generates transmit output pulses that are compliant with the ITU-T G.703 Pulse Template for 2.048Mbps (E1) rates On-Chip Pulse Shaping for both 75W and 120W Line Drivers Receiver can either be transformer or capacitively-coupled to the line Detects and Clears LOS (Loss of Signal) per ITU-T G.775 Compliant with the ITU-T G.823 Jitter Tolerance Requirements Compliant with the ITU-T G.703 EOS Overvoltage protection requirements
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Supports both Local- and Remote-Loop back Operations Logic Inputs accept either 3.3V or 5.0V levels Operates over the Industrial Temperature Range Ultra Low Power Dissipation +3.3V Supply Operation
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APPLICATIONS
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PDH Multiplexers SDH Multiplexers Digital Cross-Connect Systems DECT (Digital European Cordless Telephone) Base Stations CSU/DSU Equipment. Test Equipment
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GENERAL DESCRIPTION The XRT59L91 is an optimized single-chip analog 3.3V E1 line interface unit (LIU) fabricated using low power CMOS technology. The LIU IC consists of both a Transmitter and a Receiver function. The Transmitter accepts a TTL or CMOS level signal from the Terminal Equipment; and outputs this data to the line via bipolar pulses that are compliant to the ITU-T G.703 pulse template for E1. The Receiver accepts an attenuated bipolar line signal (from the remote terminal equipment) and outputs this data to the (near-end) terminal equipment via CMOS level signals. The receiver input can be transformer or capacitivelycoupled to the line. The receiver input is transformercoupled to the line, using the 2:1 step-down transformer. The transmitter is coupled to the line using a 1:2 step-up transformer. This same configuration is applicable for both balanced (120W ) and unbalanced (75W ) interfaces.
ORDERING INFORMATION
Part No. XRT59L91ID Package 16 LD JEDEC SOIC (300 mil) Operating Temperature Range -40C to +85C
Rev. P2.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017
XRT59L91
Preliminary
RxLO S
RTIP RRing
Recei Receive Equaliz ve Equalizer er
Peak Peak Detector/ Slice Detector/ Slicer r
LO S S LO Detect Detector or
Receive Receive O utput Interfac O utput Interface e
RxPO S RxNEG
LLoop
Loca Local Loop Loop lBack Back M UX M UX
Rem ot Rem ote Loop e Loop Back Back MM UX UX
RLoop
TTIP
PulsePulse Shaping Circui Circuit Shaping t
Transm it Transm it Input Interfac Input Interface e
TxPO S TxNEG TxClk
TRing
Figure 1. XRT59L91 Block Diagram
Rev. P2.00
2
Preliminary
PIN CONFIGURATION
1 16
XRT59L91
T xC lk T xP O S T xN E G L L oo p R L o op R xP O S R xN E G R xL O S 8
TVSS T R in g TVDD T T IP RVDD RVSS R R ing
9
R T IP
PIN DESCRIPTION Pin#
1
Symbol
TxClk
Type
I
Description
Transmitter Clock Input: If the user operates the LIU in the "clocked" mode, then the "Transmit Section" of the LIU will use the falling edge of this signal to sample the data at the TxPOS and TxNEG input pins.
Note: If the user operates the LIU in the "clockless" mode, then the Terminal Equipment should not apply a clock signal to this input pin.
2 TxPOS I Transmit - Positive Data Input: The exact signal that should be applied to this input pin depends upon whether the user intends to operate the "Transmit Section" (of the device) in the "Clocked" or "Clockless" Mode. Clocked Mode The Terminal Equipment should apply bit-wide NRZ pulses on this input pin, whenever the Terminal Equipment needs to transmit a "positivepolarity" pulse onto the line via TTIP and TRing output pins. The XRT59L91 device will sample this input pin upon the falling edge of the TCLK signal. Clockless Mode The Terminal Equipment should apply RZ pulses to this input pin, anytime the Terminal Equipment needs to transmit a "positive-polarity" pulse onto the line via TTIP and TRing output pins.
Rev. P2.00
3
XRT59L91
PIN DESCRIPTION Pin#
3
Preliminary
Symbol
TxNEG
Type
I
Description
Transmit - Negative Data Input: The exact signal that should be applied to this input pin depends upon whether the user intends to operate the "Transmit Section" (of the device) in the "Clocked" or "Clockless" Mode. Clocked Mode The Terminal Equipment should apply bit-wide NRZ pulses on this input pin, whenever the Terminal Equipment needs to transmit a "negative-polarity" pulse onto the line via TTIP and TRing output pins. The XRT59L91 device will sample this input pin upon the falling edge of the TClk signal. Clockless Mode The Terminal Equipment should apply RZ pulses to this input pin, anytime the Terminal Equipment needs to transmit a "negativepolarity" pulse onto the line via TTIP and TRing output pins.
4
LLoop
I
Local Loopback Input Select: This input pin permits the user to configure the XRT59L91 device to operate in the "Local Loopback" Mode; in order to support Diagnostic Operations. When the XRT59L91 device is operating in the Local Loopback Mode, then TTIP and TRing output signals will be (internally) routed to RTIP and RRing input signals. Setting this input pin "high" configures the XRT59L91 device to operate in the "Local Loopback" Mode. Setting this input pin "low" configures the XRT59L91 device to operate in the "Normal" Mode.
Note: Pulling both the "LLoop" and "RLoop" input pins to VDD, simultaneously, will cause the XRT59L91 device to operate in the "InCircuit Test" Mode. In this mode, all output pins will be tri-stated.
5 RLoop I Remote Loopback Input Select: This input pin permits the user to configure the XRT59L91 device to operate in the "Remote Loopback" Mode; in order to support Diagnostic Operations. When the XRT59L91 device is operating in the Remote Loopback Mode, then the RxPOS and RxNEG output pins will be (internally) routed to the TxPOS and TxNEG input pins. Setting this input pin "high" configures the XRT59L91 device to operate in the "Remote Loopback" Mode. Setting this input pin "low" configures the XRT59L91 device to operate in the "Normal" Mode.
Note: Pulling both the "LLoop" and "RLoop" input pins to VDD, simultaneously, will cause the XRT59L91 device to operate in the "InCircuit Test" Mode. In this mode, all output pins will be tri-stated.
Rev. P2.00
4
Preliminary
PIN DESCRIPTION Pin#
6
XRT59L91
Symbol
RxPOS
Type
O
Description
Receive Positive Pulse Output: This output pin will pulse "high" whenever the XRT59L91 device has received a "Positive Polarity" pulse, in the incoming line signal, at RTIP/RRing inputs. Receive Negative Pulse Output: This output pin will pulse "high" whenever the XRT59L91 device has received a "Negative Polarity" pulse, in the incoming line signal, at RTIP/RRing inputs. Receive Loss of Signal Output Indicator: This output pin toggles "high" if the XRT59L91 device has detected a "Loss of Signal" condition in the incoming line signal. Receive TIP Input: This input pin, along with RRing is used to receive the bipolar line signal from the "Remote E1 Terminal". Receive Ring Input: This input pin, along with RTIP is used to receive the bipolar line signal from the "Remote E1 Terminal". Receiver Ground Pin Receiver Power Supply Pin: 3.3V + 5% Transmit TIP Output: The XRT59L91 device will use this pin, along with TRing, to transmit a bipolar line signal, via a 1:2 step-up transformer. Transmitter Power Supply Pin: 3.3V + 5% Transmit Ring Output: The XRT59L91 device will use this pin, along with TTIP, to transmit a bipolar line signal, via a 1:2 step-up transformer. Transmitter Ground Pin
7
RxNEG
O
8
RxLOS
O
9
RTIP
I
10
RRing
I
11 12 13
RVSS RVDD TTIP
O
14 15
TVDD TRing
O
16
TVSS
-
Rev. P2.00
5
XRT59L91
Preliminary
AC ELECTRICAL CHARACTERISTICS 25C Unless otherwise specified: TA= VDD=3.3V5%, unless otherwise specified.
Parameter TClk Clock Period TClk Duty Cycle Transmit Data Setup Time Transmit Data Hold Time Transmit Data Prop. Delay Time - RZ data Mode - NRZ data Mode (clock mode) TClk Rise Time(10%/90%) TClk Fall Time(90%/10%) Receive Data Rise Time Receive Data Fall Time Receive Data Prop. Delay Receive Data Pulse Width TR TF Rtr Rtf Rpd Rxpw Symbol T1 T2 TSU THO T3 Min 47 50 30 210 Typ 488 50 50 50 160 244 Max 53 Unit ns % ns
40 40 40 40 450
ns
ns ns ns ns ns ns ns ns
DC ELECTRICAL CHARACTERISTICS 25C Unless otherwise specified: TA=-, VDD=3.3V5%, unless otherwise specified.
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage @ IOH = -4mA Output Low Voltage @ IOL = 4mA Input Leakage Current (except Input pins with pull-up resistor Input Capacitance Output Load Capacitance IL CI CL 5.0 10 25 mA pF pF Symbol VDD VIH VIL VOH VOL Min 3.13 2.0 -0.5 2.4 Typ 3.3 Max 3.46 5.0 0.8 0.4 Unit V V V V V
Power Consumption including the line power dissipation, tranmission and receive paths all active Unless otherwise specified: TA=-40 to 85C, VDD=3.3V5%, unless otherwise specified.
Parameter Power Consumption Power Consumption Power Consumption Power Consumption Power Consumption Symbol PC PC PC PC PC Min Typ 130 115 170 140 25 Max 145 130 185 155 30 Unit mW mW mW mW mW Conditions 75W load, operating at 50% Mark Density 120W load, operating at 50% Mark Density 75W load, operating at 100% Mark Density 120W load, operating at 100% Mark Density Transmitter in Powereddown mode
Rev. P2.00
6
Preliminary
RECEIVER ELECTRICAL CHARACTERISTICS TA=-40 to 85C, VDD=3.3V5%, unless otherwise specified.
Parameter Receiver Loss of Signal: Threshold to Assert Threshold to Clear Time Delay Hysteresis Receiver Sensitivity Min 12 11 10 11 Typ 20 15 5 13 Max 255 Unit dB dB bit dB dB
XRT59L91
Test Conditions Cable attenuation @ 1024KHz per ITU-G.775 Below nominal pulse amplitude of 3.0V for 120W and 2.37V for 75W applications. With -18dB interference signal added. With 6dB cable loss
Interference Margin Input Impedance Jitter Tolerance: 20Hz 700Hz 10KHz --100KHz Return Loss: 51KHz --102KHz 102KHz--2048KHz 2048KHz--3072KHz
-18 -
-14 5
-
dB KW
10 5 0.3
-
-
UIpp
14 20 16
-
-
dB dB dB
per ITU-G.703
TRANSMITTER ELECTRICAL CHARACTERISTICS TA=-40 to 85C, VDD=3.3V5%, unless otherwise specified.
Parameter AMI Output Pulse Amplitude: 75W Application 120W Application Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio Output Return Loss: 51KHz --102KHz 102KHz--2048KHz 2048KHz--3072KHz Min 2.13 2.70 224 0.95 0.95 Typ 2.37 3.00 244 1.00 1.00 Max 2.60 3.30 264 1.05 1.05 Unit V Test Conditions Use transformer with 1:2 ratio and 9.1W resistor in series with each end of primary. per ITU-G.703 per ITU-G.703
ns -
10 16 12
-
-
dB dB dB
per ETSI 300 166 and CH PTT
ABSOLUTE MAXIMUM RATINGS

Storage Temperature
-65C to + 150C -40C to + 85C -0.5V to + 6.0V

Operating Temperature

Supply Voltage
Rev. P2.00
7
XRT59L91
SYSTEM DESCRIPTION
Preliminary
1.1 The Transmit Input Interface
The XRT59L91 device is a single channel E1 transceiver that provides an electrical interface for 2.048Mbps applications. XRT59L91 includes a receive circuit that converts an ITU-T G.703 compliant bipolar signal into a TTL compatible logic levels. Each receiver also includes an LOS (Loss of Signal) detection circuit. Similarly, in the Transmit Direction, the Transmitter converts TTL compatible logic levels into a G.703 compatible bipolar signal. The Transmitter may be operated in either a "Clocked" or "Clockless" Mode. The XRT59L91 device consists of both a Transmit Section and a Receive Section; each of these sections will be discussed in detail below.
The Transmit Input Interface accepts either "clocked" or "clockless" data from the Terminal Equipment. The manner in which the Terminal Equipment should apply data to the XRT59L91 device depends upon whether the device is being operated in the "clocked" or "clockless" mode.
1.2.1 Operating the Transmitter in the Clocked Mode The user can configure the XRT59L91 device to operate in the "Clocked" mode by simply applying a 2.048MHz clock signal to the "TxClk" input pin. The XRT59L91 device contains detectioncircuitry that sense activity on the "TxClk" line. If this circuit senses activity on the "TxClk" line, then the XRT59L91 will automatically be operating in the "Clocked" Mode. In the Clocked Mode, a 2.048 mHz clock should be applied toTxClk input pin and NRZ data at the TxPOS and TxNEG input pins. The "Transmit Input Interface" circuit will sample the data, at the TxPOS and TxNEG input pins, upon the falling edge of TxClk, as illustrated below.
1.0
The Transmit Section
In general, the purpose of the "Transmit Section" (within the XRT59L91 device) is to accept TTL/CMOS level digital data (from the Terminal Equipment), and to encode it into a format such that it can: 1. Be efficiently transmitted over coaxial- or twistedpair cable at the E1 data rate; and 2. Be reliably received by the Remote Terminal Equipment at the other end of the E1 data link. 3. Comply with the ITU-T G.703 pulse template requirements, for E1 applications. The circuitry that the Transmit Section (within the XRT59L91 device) uses to accomplish this goal is discussed below. The Transmit Section of the XRT59L91 device consists of the following blocks:
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Transmit Input Interface Pulse Shaping Block
Rev. P2.00
8
Preliminary
XRT59L91
tSU
tHO
TxPO S
TxNEG
TClk
Figure 2. Illustration on how the XRT59L91 Device Samples the data on the TXPOS and TXNEG input pins In general, if the XRT59L91 device samples a "1" on the TxPOS input pin, then the "Transmit Section" of the device will ultimately generate a positive polarity pulse via the TTIP and TRing output pins (across a 1:2 transformer). Conversely, if the XRT59L91 device samples a "1" on the "TxNEG" input pin, then the "Transmit Section" of the device will ultimately generate a negative polarity pulse via the TTIP and TRing output pins (across a 1:2 transformer). 1.2.1 Operating the Transmitter in the "Clockless" Mode The user can configure the XRT59L91 device to operate in the "Clockless" mode by doing the following:
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Not applying a clock signal to the TXClk input, and either pulling this pin to VDD or letting it float.
By applying RZ (Return to Zero) data to the TxPOS and TxNEG input pins, as illustrated below.
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B it P e rio d D a ta 1
R Z P u lse w id th sh o u ld co n fo rm to G .7 0 3 T e m p la te
N o p u lse is to b e a p p lie d in th e se co n d h a lf o f th e b it p e rio d 1 1 0 1
1
0
T xP O S
T xN E G
T xC lk
N o A ctivity in T xC lk L in e
Figure 3. IIlustration on how the Terminal Equipment should apply data to the "Transmit Section" of the XRT59L91 Device, when operating in the "Clockless" Mode
Rev. P2.00
9
XRT59L91
Preliminary
1.3 The Pulse Shaping Circuit
Figure 3, indicates that when the user is operating the XRT59L91 device in the "Clockless" Mode, then the Terminal Equipment must do the following.
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Not apply a signal on the "TxClk" line. When applying a pulse (to either the TxPOS or TxNEG input pin), apply an RZ pulse to the appropriate input pin. This RZ pulse should only have a width of one-half the bit-period. Addition, the RZ pulse should occupy only the first half of the bit-period. The TxPOS and TxNEG input pins must be at 0V, during the second half of every bitperiod.
The purpose of the "Transmit Pulse Shaping" circuit is to generate "Transmit Output" pulses that comply with the ITU-T G.703 Pulse Template Requirements for E1 Applications. An illustration of the "ITU-T G.703 Pulse Template Requirements" is presented below in Figure 4.
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269ns (244 + 25)
V = 100%
194ns
Nominal Pulse
50%
244ns 219ns (244 - 25) 10% 20%
0%
10%
Figure 4. Illustration of the ITU-T G.703 Pulse Template for E1 Application
Rev. P2.00
10
Preliminary
With input signal as described above, the XRT59L91 device will take each mark (which is provided to it via the "Transmit Input Interface" block, and will generate a pulse that complies with the pulse template, presented in Figure 4 (when measured on the secondary-side of the Transmit Output Transformer). 1.2
XRT59L91
Interfacing the Transmit Section of the XRT59L91 device to the Line
ITU-T G.703 specifies that the E1 line signal can be transmitted over coaxial cable and terminated with 75W or transmitted over twisted-pair and terminated with 120W . In both applications (e.g., 75W or 120W ), the user is advised to interface the Transmitter to the Line, in the manner as depicted in Figures 5 and 6, respectively.
U 1
T xP O S
2 T xP O S T T IP
1 3
1
R 1 9. 1
2
1 3
1: 2
J 1 BN C 5 1
T xN E G
T xN E G 2 4 8 PE65835 2
T xL in e C lk
1 T xC lk T R in g
1 5
1
R 2 9. 1
XRT59L91
Figure 5. Illustration of how to interface the Transmit Section of the XRT59L91 device to the Line (for "75W " Applications) W
Rev. P2.00
11
XRT59L91
U1
Preliminary
T xP O S
2 T xP O S T T IP
13
1
R1 9 .1
2
1 3 T xN E G 4
1 :2
5
T T IP
T xN E G
8 T R IN G P E -65 8 35
T xL in eC lk
1 T xC lk T R ing
15
1
R2 9 .1
2
X R T 59 L 9 1
Figure 6. Illustration of how to interface the Transmit Section of the XRT59L91 device to the Line (for "120W " Applications) W
Notes: 1. Figures 5 and 6 indicate that for both "75W and "120W " applications, the user should connect a 9.1W resistor, in series, between the TTIP/TRing outputs and the transformers. 2. Figure 5 and 6 indicate that the user should a "1:2 STEP-UP" Transformer.
Rev. P2.00
12
Preliminary
Transmit Transformer Recommendations
Parameter Turns Ratio Primary Inductance Isolation Voltage Leakage Inductance Value 1:2
XRT59L91
The Following Transformers Are Recommended For Use:
Part Num ber PE-65835 TTI 7154-R TG26-1205 Vendor Pulse Transpower Technologies, Inc. HALO Isolation Package Type
Note: More transformers will be added to this list as we take the time to evaluate these transformers.
Magnetic Supplier Information
Pulse Corporate Office 12220 World Trade Drive San Diego, CA 92128 Tel: (619)-674-8100 FAX: (619)-674-8262 Europe 1 & 2 Huxley Road The Surrey Research Park Guildford, Surrey GU2 5RE United Kingdom Tel: 44-1483-401700 FAX: 44-1483-401701 Asia 150 Kampong Ampat #07-01/02 KA Centre Singapore 368324 Tel: 65-287-8998 FAX: 65-280-0080
Transpower Technologies Corporate Office 9410 Prototype Drive, Ste #1 Reno, NV 89511 Tel: (800)511-7308 or (775)852-0140 Fax: (775)852-0145 www.trans-power.com
HALO Electronics HALO Electronics P.O. Box 5826 Redwood City, CA 94063 Tel: (650)568-5800 FAX: (650)568-6161
Rev. P2.00
13
XRT59L91
Preliminary
2.0 The Receive Section The Receive Section of the XRT59L91 device consists of the following blocks:
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2.1 Interfacing the Receive Section to the Line The design of the XRT59L91 device permits the user to transformer-couple or capacitive-couple the Receive Section to the line. Additionally, as mentioned earlier, the specification documents for E1 specify 75W termination loads, when transmitting over coaxial cable, and 120W loads, when transmitting over twistedpair. Figures 7 through 9 present the various methods that the user can employ in order to interface the Receiver (of the XRT59L91 device) to the line.
The "Receive Equalizer" block The "Peak Detector" and "Slicer" block The "LOS Detector" block The "Receive Output Interface" block
U1
R xP O S
6
R xP O S
R T IP
9 J1 BNC 1 RL 2 1 8.7 4 1 8 P E-6 58 3 5 1 :2 5 1 2
R xN E G
7
R xN E G
L oss o f Sig na l
8
R xL O S
R R in g
10
X RT5 9L91
Figure 7. Recommended Schematic for Interfacing the Receive Section of the XRT59L91 Device to the Line for 75W Applications (Transformer-Coupling) W
Rev. P2.00
14
Preliminary
U1
XRT59L91
R xP O S
6 R xP O S R T IP
9
1
1 :2
5
1
R T IP
R xN E G
7 R xN E G
RL 3 0 .1 4 8 P E -6 5 8 3 5 2 R R IN G
L o s s o f S ig n a l
8 R xL O S R R in g
10
XRT59L91
Figure 8. Recommended Schematic for Interfacing the Receive Section of the XRT59L91 Device to the Line for 120W Applications (Transformer-Coupling) W
Note: Figures 7 and 8 indicate that the user should use a "2:1 STEP-DOWN" transformer, when interfacing the re ceiver to the line.
U1
C1 R xP O S 6 R xP O S R T IP 9 1 0.1uF 2 1 R1 37 .4 2 R T IP
1
R xN E G
7
R xN E G
R2 37 .4
2
C2 Lo ss of S ig nal 8 R xLO S R R in g 0.1uF 10 1 2 R R IN G
XRT59L91
Figure 9. Recommended Schematic for Interfacing the Receive Section of the XRT59L91 Device to the Line for 75W Applications (Capacitive-Coupling) W
Rev. P2.00
15
XRT59L91
2.2 The "Receive Equalizer" Block
Preliminary
After the XRT59L91 device has received the incoming line signal, via the RTIP and RRing input pins, the first block that this signal will pass through is the Receive Equalizer block. As the line signal is transmitted from a given "Transmitting" terminal, the pulse shapes (at that location) are basically "square". As this line signal travels from the "transmitting terminal" (via the coaxial cable or twisted pair) to the receiving terminal, it will be subjected to "frequency-dependent" loss. In other words, the higher frequency components of the signal will be subjected to a greater amount of attenuation than will the lower frequency components. If this line signal travels over reasonably long cable lengths, then the shape of the pulses (which were originally square) will be distorted and cause inter-symbol interference to increase. The purpose of this block is to equalize the incoming distorted signal, due to cable loss. In essence, the Receive Equalizer block accomplishes this by subjecting the received line signal to "frequency-dependent"
amplification (which attempts to counter the frequency-dependent loss that the line signal has experienced). By doing this, the Receive Equalizer is attempting to restore the shape of the line signal so that the received data can be recovered reliably. 2.3 The "Peak Detector and Slicer Block
After the incoming line signal has passed through the Receive Equalizer block, it will be routed to the "Slicer" block. The purpose of the "Slicer" block is to quantify a given bit-period (or symbol) within the incoming line signal as either a "1" or a "0". 2.4 The "LOS Detector" Block
The LOS Detector block, within the XRT59L91 was specifically designed to comply with the "LOS Declaration/Clearance" requirements per ITU-T G.775. As a consequence, the XRT59L91 device will declare an LOS Condition, (by driving the "RxLOS" output pin "high") if the received line signal amplitude drops to - 35dB or below. Further, the XRT59L91 device will clear the LOS Condition if the signal amplitude rises back up to -12dB or above. Figure 10 presents an illustration of G.775 spec for declaring and clearing LOS.
0 dB
Maximum Cable Loss for E1 LOS Signal Must be Cleared -6 dB
-9dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
Figure 10. Illustration of G.775 Spec.
Rev. P2.00
16
Preliminary
Timing Requirements associated with Declaring and Clearing the LOS Indicator. The XRT59L91 device was designed to meet the ITUT G.775 specification timing requirements for declaring and clearing the LOS indicator. In particular, the XRT59L91 device will declare LOS, between 10 and 255 UI (or E1 bit-periods) after the actual time the LOS condition occurred. Further, the XRT59L91 device will
XRT59L91
clear the LOS indicator within 10 to 255 UI after restoration of the incoming line signal. Figure 11 illustrates the LOS Declaration and Clearance behavior, in response to first, the "Loss of Signal" event and then afterwards, the restoration of the signal.
A ctu a l O ccuL O S ce o f rre n C o n d itio n
L in e S ig n a l is R e sto re d
R X IN
10 U I
255 U I
T im e R a n g e Lfo rS O D e cla ra tio n
10 U I
255 U I
L O S O u tp u t P in
0 UI
0 UI
G .7 7 5 C o m p lia n ce T im e R a n g e Lfo rS O C le a ran ce G .7 7 5 C o m p lia n ce
N ote : F o r E 1 , 1 U I = 4 8 8 n s
Figure 11. The Behavior of the LOS Output Indicator, in response to the Loss of Signal, and the Restoration of the Signal
2.5
The "Receive Output Interface" Block RRing input pins, then the Receive Output Interface will output a pulse at the "RxPOS" output pin. Similarly, if the "Receive Section" of the XRT59L91 device has received a "Negative-Polarity" pulse, via the RTIP and RRing input pins, then the Receive Output Interface will output a pulse at the "RxNEG" output pin.
The purpose of the "Receive Output Interface" block is to interface directly with the "Receiving Terminal Equipment". The "Receive Output Interface" block outputs the data (which has been recovered from the incoming line signal) to the "Receive Terminal Equipment" via the "RxPOS and RxNEG output pins. If the "Receive Section" of the XRT59L91 device has received a "Positive-Polarity" pulse, via the RTIP and
Rev. P2.00
17
XRT59L91
3.0 Diagnostic Features
Preliminary
Mode) into the XRT59L91 device via the TxPOS, TxNEG and TxCLK input pins. This data will be processed through the "Transmit Terminal Input Interface" and the "Pulse Shaping" circuit. Finally, this data will be output to the line via the TTIP and TRing output pins. Additionally, this data (which is being output via the TTIP and TRing output pins) will be looped back into the "Receive Equalizer" block. As a consequence, this data will also be processed through the entire "Receive Section" of the XRT59L91 device. After this "post-loopback" data has been processed through the "Receive Section" it will output, to the "Near-End Receiving Terminal Equipment" via the "RxPOS and RxNEG output pins. Figure 12, illustrates the path that the data takes (within the XRT59L91 device), when the chip is configured to operate in the "Local Loop-back" Mode.
In order to support diagnostic operations, the XRT59L91 supports the following loopback modes:
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Local Loopback Remote Loopback
Each of these loopback modes will be discussed below. 3.1 The Local Loop-Back Mode
When the XRT59L91 device is configured to operate in the "Local Loop-back" Mode, the XRT59L91 device will ignore any signals that are input to the RTIP and RRing input pins. The "Transmitting Terminal Equipment" will transmit data (and clock, for "Clocked"
R xLO S
R TIP
R ece ive E qua lizer
P eak D etector/ S licer
LO S D etector
R ece ive O utput Interface
R xP O S
R R ing
R xN E G
LLoop
Local Loop B ack MUX
Local Loop B ack P ath
R em ote Loop B ack MUX
R Loop
TTIP P ulse S haping C ircu it TR ing Tra nsm it Input Interface
TxP O S TxN E G TxC lk
Figure 12. Illustration of the "Local Loop-back" within the XRT59L91 Device
Rev. P2.00
18
Preliminary
The user can configure the XRT59L91 device to operate in the "Local Loop-back" Mode, by pulling the "LLoop" input pin (pin 4) to VDD. 3.2 The Remote Loop Back Mode
XRT59L91
When the XRT59L91 device is configured to operate in the "Remote Loop-back" Mode, the XRT59L91 device will ignore any signals that are input to the TxPOS and TxNEG input pins. The XRT59L91 device will receive the incoming line signals, via the RTIP and RRing input pins. This data will be processed through the entire Receive Section (within the XRT59L91) and will output to the "Receive Terminal Equipment" via the
"RxPOS" and "RxNEG" output pins. Additionally, this data will also be internally looped back to the "Transmit Input Interface" block within the "Transmit Section". At this point, this data will be routed through the remainder of the "Transmit Section" of the XRT59L91 device and will be transmitted out onto the line via the "TTIP" and "TRing" output pins. Figure 13, illustrates the path that the data takes (within the XRT59L91 device) when the chip is configured to operate in the "Remote Loop-back" Mode.
R xLO S
R TIP R eceive R eceive E q ualize r E q ualize r P e ak D ete ctor/ P e ak D ete ctor/ S licer S licer LO S LO S D etector D etector R eceive O utpu t R eceive O utpu t In terface In terface
R xP O S
R R ing
R xN E G
LL oop
Lo cal Lo cal Lo op B ack Lo op B ack MUX MUX
R em o te Loop B a ck P a th
R em o te R em o te Lo op B ack Lo op B ack MUX MUX
R Loop
TTIP P u lse S ha ping P u lse S ha ping C ircuit C ircuit TR ing Transm it In put Transm it In put In terface In terface
TxP O S TxN E G TxC lk
Figure 13. Illustration of the "Remote Loop-back" path, within the XRT59L91 Device
It should be noted that during "Remote Loop-back" operation, any data which is input via the RTIP and
RRING input pins, will also be output to the Terminal Equipment, via the RxPOS and RxNEG output pins.
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XRT59L91
4.0 Shutting off the Transmitter
Preliminary
Method 1: Connect the Transmit Data input pins (e.g., TxPOS and TxNEG) to a logic "1"; or allow them to float. (These input pins have an internal "pull-up" resistor). Method 2: Connect the "TxClk" input pin to a logic "0" (e.g., GND) and continue to apply data via the TxPOS and TxNEG input pins.
The XRT59L91 device permits the user to shut the "Transmit Driver" within the Transmit Section of the chip. This feature can be useful for system redundancy design considerations or during diagnostic testing. The user can activate this feature by either of the following ways.
NRZ M ode (Clock M ode) T1 T2 TR TF
T C lk
TS U
TH O
T xP O S o r TNEG
T3
T XPW V TX O U T
T T IP / T R ing
RZ M ode (None-Clock M ode)
T xP O S o r TNEG T3 T T IP / T R ing
T XPW V TX O U T
Figure 14. Transmit Timing Diagram
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Preliminary
XRT59L91
R T IP / R R in g R p d R xp w
R xP O S R tr R tf
R xN E G
Figure 15. Receive Timing Diagram
APPLICATIONS INFORMATION Figures 16, 17 and 18, provide example schematics on how to interface the XRT59L91 device to the line, under the following conditions:
l
l
l
Receiver is Transformer-coupled to a 75W unbalanced line. Receiver is Transformer-coupled to a 120W balanced line. Receiver is Capacitive-coupled to a 75W unbalanced line
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XRT59L91
U1
Preliminary
T xP O S
2
T xP O S
T TIP
13
1
R1 9 .1
2 1 1 :2 5 1
J1 BNC
T xN E G
3
T xN E G 4 8 P E -6 5 83 5
2
T xLin eC lk
1
T xC lk
T R in g
15
1
R2 9 .1
2
R xP O S
6
R xP O S
R TIP
9 1 R3 1 1 :2 1 8.7 5 1
J2 BNC
R xN E G
7
R xN E G 2
2
4 L oss o f S ig n a l 8 R xL O S R R in g 10
8 P E -6 5 83 5
XRT59L91
Figure 16. Illustration on how to interface the XRT59L91 Device to the Line (Receiver is Transformer-coupled to a 75W unbalanced line) W
Rev. P2.00
22
Preliminary
U1
XRT59L91
Tx P O S
2
Tx P O S
TT IP
13
1
R1 9 .1
2 1 1 :2 5 TT IP
Tx N E G
3
Tx N E G 4 8 TR IN G
Tx LIn e C lk
1
Tx C lk
TR in g
15
1
R2 9 .1
2
P E -6 5 83 5
RxPOS
6
RxPOS
R T IP
9 2 R3 1 1 :2 3 0.1 4 1 8 R R IN G 5 R T IP
RxNEG
7
RxNEG
L os s of S ign a l
8
R x LO S
R R in g
10
P E -6 5 83 5
XRT59L91
Figure 17. Illustration on how to interface the XRT59L91 Device to the Line (Receiver is Transformer-coupled to a 120W balanced line) W
Rev. P2.00
23
XRT59L91
U1
Preliminary
T xP O S
2
T xP O S
T TIP
13
1
R1 9 .1
2 1 1 :2 5 1
J1 BNC
T xN E G
3
T xN E G 4 8
2
T xL in e C lk
1
T xC lk
T R ing
15
1
R2 9 .1
2
P E -6 5 83 5
J2 C1 R xP O S 6 R xP O S R TIP 9 1 2 0 .1 u F R xN E G 7 1 R3 3 7 .4 1 2 R4 3 7 .4 C2 L o ss o f S ig n al 8 R xL O S R R ing 10 1 2 0 .1 u F XRT59L91 2 2 1 BNC
R xN E G
Figure 18. Illustration on how to interface the XRT59L91 Device to the Line (Receiver is Capacitive-coupled to a 75W unbalanced line) W
Rev. P2.00
24
Preliminary
XRT59L91
Rev. P2.00
25
XRT59L91
Preliminary Notes
Rev. P2.00
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Preliminary Notes
XRT59L91
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XRT59L91
Preliminary
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1999 EXAR Corporation Datasheet October 1999 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. P2.00
28

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